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[AKD4373-B] a kd4373-b a k4373 evaluation board rev.1 general description the akd4373 is an evaluation board for 24bit dac with headphone amplifier and a monaural speaker driver, ak4373. the akd4373 has the interface with akemd?s adc evaluation boar ds. therefore, it?s easy to evaluate the ak4373. the adk4373 also has the digital audi o interface and can achieve the interface with digital audi o systems via opt-connector. ? ordering guide AKD4373-B --- evaluation board for ak4373 (cable for connecting with printer port of ib m-at compatible pc and control software are packed with this. this control software does not operate on windows nt.) function ? compatible with 2 types of interface - direct interface with akemd?s a/d converter evaluation boards - on-board ak4116 as dir which accepts optical input ? 10pin header for serial control interface ? mini-jack for external stereo hp and a monaural speaker gnd ak4116 ( dir ) opt in (port1) dsp 10pin header (port2) ak4373 lout regulator vcc (5.0v) (3.3v) rout control data 10pin header (port3) l/rout min+/- / hpl / hpr spk hp figure 1. akd4373 block diagram * circuit diagram and pcb layout are attached at the end of this manual. 2008/07 - 1 -
[AKD4373-B] board outline chart ? outline chart AKD4373-B rev.1 evaluation board akm gnd +5v min+/- j3 l/r out j4 j2 hp j1 spk/hpr port3 1 10 6 5 10 5 6 port1 tor x141 u2 x1 u4 74avc8t245 u3 74hc14 sw1 u5 ak4373 1 5 port2 ak4116 6 figure 2. AKD4373-B outline chart ? comment (1) j1, j2, j3, j4 (mini-jack) j1 (spk/hpr-jack): an analog signal output jack. the signal is output to spk or hpr pin. j2 (hp-jack): an analog signal output jack. the signal is output to hp or hpl pin. j3 (mic-jack): an analog signal input jack. the signal is input to mic pin. j4 (l/rout-jack): an analog signal output jack. the signal is output to l/rout pin. (2) +5v, gnd +5v-jack: the power supply connector. gnd-jack: the ground connector. (3) port1 (optical connecter) port1 (input): optical digital signal (spdif, fs: 32~48khz) is input to the ak4116. (4) port2, port3 (10 pin header) port2 (10 pin header): the clock and data can be input and output with this connector. port3 (10 pin header): control port. connect the bundled cable into this port. 2008/07 - 2 -
[AKD4373-B] ? operation sequence 1) set up the power supply lines. name color voltage comments attention +5v red +5v input to regulator this jack is always needed. power line gnd black 0v for ground this jack is always needed. table 1. set up power supply lines * setting of power supply ?dvdd?: jp10 (dvdd-reg) open: it supplies ? dvdd? from the outside to right pin. short: it supplies ?dvdd? from the regulator (3.3v) . each supply line should be distributed from the power supply unit. 3.3v is supplied to ak4373 via the regulator. 2) set up the evaluation mode, jumper pins. (see the followings.) 3) power on. the ak4373 and ak4116 should be resets once bringing sw1 (dac/dir-pdn) ?l? upon power-up. ? evaluation mode when evaluating the ak4373 using the port1 (ak4116), it is possible to use the initial setting of the audio interface format (24bit msb justified). the ak4116 operates at fs of 32khz or more. if the fs is slower than 32khz, any other evaluation mode should be used. when inputting the data from the port2, the ak4373? s audio interface format should be set to correspond the input data?s audio interface fo rmat. refer to the ak4373?s datasheet. applicable evaluation mode (1) pll master mode (2) pll slave mode (2-1) pll reference clock: mcki pin (2-2) pll reference clock: bick or lrck pin (3) external slave mode (3-1) evaluation using dir (opt ical link) of ak4116 (3-2) evaluation connecting akd4373 with external dsp (4) external master mode 2008/07 - 3 -
[AKD4373-B] (1) pll master mode port2 (dsp) is used. nothing should be connected to port1 (dir). bick and lrck are supplied from port2. it is possible to evaluate at various samp ling frequencies using built-in the ak4373?s pll. ak4373 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz,12mhz,12.288mhz 13.5mhz,24mhz,25mhz,27mhz mclk figure 3. pll master mode the system clock should be connected to mclk of port2. sdti of port2 should be connected to sdto of dsp. the jp16 (lrck2) and jp17 (bick2)?s right side should be connected to lrck and bick of dsp. in case of supplying mcko to dsp, the test pin (mcko) should be connected to mclk of dsp. set up the jumper pins. jp17 bick2 jp16 lrck2 jp12 bick jp13 lrck mclk jp11 sdto jp14 2008/07 - 4 -
[AKD4373-B] (2) pll slave mode (2-1) pll reference clock: mcki pin ak4373 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs 256fs/128fs/64fs/32fs 11.2896mhz,12mhz,12.288mhz 13.5mhz,24mhz,25mhz,27mhz mclk figure 4. pll master mode (pll reference clock: mcki pin) port2 (dsp) is used. nothing should be connected to port1 (dir). mcko is needed for a synchronous signal of bick and lrck. mclk, bick, lrck and sdata are supplied from port2. the test pin (mcko) should be connected to mclk of dsp. set up the jumper pins. jp17 bick2 jp16 lrck2 jp12 bick jp13 lrck mclk jp11 sdto jp14 2008/07 - 5 -
[AKD4373-B] (2-2) pll reference clock: bick or lrck pin ak4373 dsp or p mcko bick lrck sdata bclk lrck sdto mcki 1fs 32fs or 64fs figure 5. pll master mode (pll reference clock : bick or lrck pin) port2 (dsp) is used. nothing should be connected to port1 (dir). bick, lrck and sdata are supplied from port2. set up the jumper pins. jp17 bick2 jp16 lrck2 jp12 bick jp13 lrck mclk jp11 sdto jp14 2008/07 - 6 -
[AKD4373-B] (3) external slave mode the ak4373?s register should be set to ext slave mode. mcki frequency should be set to the same as the specification of dsp or dir. about the ak4373?s register definitions, refer to datasheet of the ak4373. ak4373 dsp or p mcki bick lrck sdata bclk lrck sdto mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 6. external slave mode (3-1) evaluation using dir (opt ical link) of ak4116 port1 (dir) is used. nothing should be connected to port2 (dsp). set up the jumper pins. jp17 bick2 jp16 lrck2 jp12 bick jp13 lrck mclk jp11 sdto jp14 (3-2) evaluation connecting akd4373 with external dsp port2 (dsp) is used. nothing should be connected to port1 (dir). set up the jumper pins. jp17 bick2 jp16 lrck2 jp12 bick jp13 lrck mclk jp11 sdto jp14 2008/07 - 7 -
[AKD4373-B] (4) external master mode the ak4373?s register should be set to ext master mode . mcki frequency should be set to the same as dsp?s specification. about the ak4373?s register definitions, refer to datasheet of the ak4373. ak4373 dsp or p mcki bick lrck sdata bclk lrck sdto mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 7. ext master mode port2 (dsp) is used. nothing should be connected to port1 (dir). the system clock should be connected to mclk of port2. sdti of port2 should be connected to sdto of dsp. the jp16 (lrck2) and jp17 (bick2)?s right side should be connected to lrck and bick of dsp. set up the jumper pins. jp17 bick2 jp16 lrck2 jp12 bick jp13 lrck mclk jp11 sdto jp14 2008/07 - 8 -
[AKD4373-B] ? the function of the toggle sw upper-side is ?h? and lower-side is ?l?. [sw1] (dac/dir_pdn): power down of ak4373 and ak4116. keep ?h? during normal operation. ? indication for led [led1] (erf): monitor int0 pin of the ak4116. led turns on when some error has occurred to ak4116. 2008/07 - 9 -
[AKD4373-B] ? serial control the ak4373 can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port3 (up -if) with pc by 10 wire flat cable packed with the akd4373. 10pin header csn 10 wire flat cable cclk cdti 10pin connector pc connect a kd4373 1 10 5 6 port3 figure 8. connect of 10 wire flat cable (1) 3-wire serial control mode the jumper pins should be set to the followings. jp2 i2c_sel jp9 sda i2c 3-wire jp10 cad0 (2) i 2 c-bus control mode the jumper pins should be set to the followings. (2-1) in case of using cad0=0 (device address bit). jp2 i2c_sel jp9 sda i2c 3-wire jp10 cad0 (2-2) in case of using cad0=1 (device address bit). jp2 i2c_sel jp9 sda i2c 3-wire jp10 cad0 2008/07 - 10 -
[AKD4373-B] ? input / output circuit (1) input circuit min+/- circuits min+ min- + c14 1u + c13 1u r10 20k r11 20k j3 min+/ 6 4 3 - figure 9. min+/- input circuits (2) output circuit 1) lout/rout output circuit lout rout j 4 l /r out 4 6 3 + c16 1u r13 47k r15 220 + c15 1u r12 47k r14 220 figure 10. lout/rout output circuits 2008/07 - 11 -
[AKD4373-B] 2) hp output circuits a. single-ended mode hpl hpr hvcm jp3 hpr cap-less j2 h p 4 6 3 jp4 hp-sel r9 0 jp5 hpl cap-less gnd hvcm r8 0 + c11 47u + c12 47u figure 11. hp output circuit (single-ended mode) set up the jumper pins. jp5 hpl cap-less jp4 hp-sel hvcm gnd jp3 hpr cap-less b. differential mode hpl+ hpl- hpr+ hpr- j1 hp r 4 6 3 jp5 hpl cap-less jp3 hpr cap-less j2 hp l 4 6 3 jp2 hp/spk-sel tp7 hpl+ 1 tp8 hpl- 1 tp9 hpr+ 1 tp10 hpr- 1 r9 0 jp4 hp-sel gnd hvcm spn hp r8 0 + c11 47u + c12 47u figure 12. hp output circuit (differential mode) set up the jumper pins. jp5 hpl cap-less jp4 hp-sel hvcm gnd jp3 hpr cap-less jp2 hp/spk-sel hp spn 2008/07 - 12 -
[AKD4373-B] c. pseudo cap-less mode hpl+ hpl- hvcm jp5 hpl cap-less jp3 hpr cap-less j2 h p 4 6 3 jp2 hp/spk-sel r9 0 jp4 hp-sel gnd hvcm spn hp r8 0 + c11 47u + c12 47u figure 13. hp output circuit (pseudo cap-less mode) set up the jumper pins. jp5 hpl cap-less jp4 hp-sel hvcm gnd jp3 hpr cap-less jp2 hp/spk-sel hp spn 2008/07 - 13 -
[AKD4373-B] 3) speaker output circuit spp spn j1 spk 4 6 3 jp2 hp/spk-sel spn hp figure 14. speaker output circuit set up the jumper pins. jp2 hp/spk-sel hp spn ? akemd assumes no responsibility for the troubl e when using the above circuit examples. 2008/07 - 14 -
[AKD4373-B] control software manual ? set-up of evaluation board and control software 1. set up the akd4373 according to previous term. 2. connect ibm-at compatible pc with akd4373 by 10-line type flat cable (packed with akd4373). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not n eeded. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?ak4373 evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?akd4373.exe? to set up the control program. 5. then please evaluate acco rding to the follows. ? operation flow keep the following flow. 1. set up the control program acco rding to explanation above. 2. click ?port reset? button. 3. click ?write default? button. ? explanation of each buttons 1. [port reset]: set up the usb interface boa rd (akdusbif-a) when using the board. 2. [write default]: initialize the register of ak4373. 3. [all write]: write all registers that is currently displayed. 4. [function1]: dialog to write data by keyboard operation. 5. [function2]: dialog to write data by keyboard operation. 6. [function3]: the sequence of register setting can be set and executed. 7. [function4]: the sequence that is created on [function3] can be assigned to buttons and executed. 8. [function5]: the register setting that is created by [save] function on main window can be assigned to buttons and executed. 9. [save]: save the current register setting. 10. [open]: write the saved values to all register. 11. [write]: dialog to write data by mouse operation. ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet. 2008/07 - 15 -
[AKD4373-B] ? explanation of each dialog 1. [write dialog] : dialog to write data by mouse operation there are dialogs corres ponding to each register. click the [write] button corresponding to each register to se t up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to ak4373 click [ok] button. if not, click [cancel] button. 2. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. if you want to write the input data to ak4373 click [ok] button. if not, click [cancel] button. 3. [function2 dialog] : dialog to evaluate digital volume. there are dialogs corresponding to register of 09h, 0ah, 0ch and 0dh. address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is wr itten to ak4373 by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not re turn to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to ak4373 click [ok] button. if not, click [cancel] button. 2008/07 - 16 -
[AKD4373-B] 4. [save] and [open] 4-1. [save] all of current register setting values displayed on the main window are saved to the file. the extension of file name is ?akr?. (1) click [save] button. (2) set the file name and click [save] button. the extension of file name is ?akr?. 4-2. [open] the register setting values saved by [save] are written to the ak4373. the file type is the same as [save]. (1) click [open] button. (2) select the file (*.ak r) and click [open] button. 2008/07 - 17 -
[AKD4373-B] 5. [function3 dialog] the sequence of register setting can be set and executed. (1) click [f3] button. the default setting sequence dac->hp (3d=off) is displayed. jump to (3) below if the default setting sequence is used. go to (2) if the other setting sequence is required. (2) set the control sequence. set the address, data and interval time. set ?-1? to th e address of the step where the sequence should be paused. (3) click [start] button. then this sequence is executed. the sequence is paused at the step of interval = ?-1?. click [start] button, the sequence restarts from the paused step. this sequence can be saved and opened by [save] and [open] button on the function3 window. the extension of file name is ?aks?. figure 15. window of [f3] 2008/07 - 18 -
[AKD4373-B] 6. [function4 dialog] the sequence file (*.aks) saved by [function3] can be liste d up to 10 files, assigned to buttons and then executed. when [f4] button is clicked, the window as shown in figure 16 opens. figure 16. [f4] window 2008/07 - 19 -
[AKD4373-B] 6-1. [open] buttons on left side and [start] buttons (1) click [open] button and select the seque nce file (*.aks) saved by [function3]. the sequence file name is displayed as shown in figure 17 . (in case that the selected sequence file name is ?dac_stereo_on.aks?) figure 17. [f4] window (2) (2) click [start] button, then the sequence is executed. 6-2. [save] and [open] buttons on right side [save]: the name assign of sequence file displayed on [function4] window can be saved to the file. the file name is ?*.ak4?. [open]: the name assign of sequence file (*.ak4) saved by [save] is loaded. 6-3. note (1) this function doesn't support the pause function of sequence function. (2) all files used by [save] and [open] function on right side need to be in the same folder. (3) when the sequence is changed in [function3], the sequence file (*.aks) should be loaded again in order to reflect the change. 2008/07 - 20 -
[AKD4373-B] 7. [function5 dialog] the register setting file (*.akr) saved by [save] function on main window can be listed up to 10 files, assigned to buttons and then executed. when [f5] button is clicked, the window as shown in figure 18 opens. figure 18. [f5] window 7-1. [open] buttons on left side and [write] button (1) click [open] button and select the register setting file (*.akr). the register setting file name is displayed as shown in figure 19 . (in case that the selected file name is ?dac_output.akr?) (2) click [write] button, then the register setting is executed. 2008/07 - 21 -
[AKD4373-B] figure 19. [f5] window (2) 7-2. [save] and [open] buttons on right side [save]: the name assign of register setting file displaye d on [function5] window can be saved to the file. the file name is ?*.ak5?. [open]: the name assign of register setting file (*.ak5) saved by [save] is loaded. 7-3. note (1) all files used by [save] and [open] function on right side need to be in the same folder. (2) when the register setting is changed by [save] butt on on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. 2008/07 - 22 -
[AKD4373-B] 8. [filter dialog] this dialog can easily set the ak4373?s programmable filter. a calculation of a coefficient of digital programmable filter such as hpf, eq filter ,a write to a register and check frequency response. window to show to figure 20 opens when push a [filter] button. figure 20. [filter] window 2008/07 - 23 -
[AKD4373-B] 8-1. setting of a parameter (1) please set a parameter of each filter. item contents setting range sampling rate sampling frequency (fs) 7350hz fs 48000hz fil3 cut off frequency stereo separation emphasis filter cut off frequency fs/10000 cut off frequency (0.497 * fs) filter type type of stereo separation emphasis filter lpf or hpf gain gain of stereo se paration emphasis filter ?10db gain 0db hpf cut off frequency high pass filter cut off frequency fs/10000 cut off frequency (0.497 * fs) lpf cut off frequency low pass filter cut off frequency fs/20 cut off frequency (0.497 * fs) eq for gain compensation (eq) pole frequency pole frequency fs/10000 pole frequency (0.497 * fs) zero-point frequency zero -point frequency fs/10000 zero-point frequency (0.497 * fs) gain gain 0db gain +12db 5 band equalizer eq1-5 center frequency eq1-5 center frequency 0hz center frequency < (0.497 * fs) eq1-5 band width eq1-5 band width ( note 1 ) 1hz band width < (0.497 * fs) eq1-5 gain eq1-5 gain ( note 2 ) -1 gain < 3 note 1. bandwidth where the gain gap is 3db compared with center frequency. note 2. when a gain is smaller than ?0?, eq1-5 becomes a notch filter. (2) please set on/off of filter with check buttons of ?fil3?, ?eq?, ?lpf?, ?hpf?, ?eq1?, ?eq2?, ?eq3?, ?eq4?, ?eq5?. when the button is checked, filter becomes on. when ?notch filter auto correction? is checked, automatic compensation is executed for center frequency of notch filter. (?cf. 8-4. automatic compensation for center frequency of a notch filter?) figure 21. filter on/off setting button 2008/07 - 24 -
[AKD4373-B] 8-2. a calculation of a register a register setting values are displayed when [register setting] button is clicked. when any value is set to out or range, error message is displayed, and a calculation of register setting is not executed. figure 22. a register setting calculation result in the following cases, a register set values are updated. (1) when [register setting] button was pushed. (2) when [frequency response] button was pushed. (3) when [update] button was pushed on a frequency characteristic indication window. (4) when set on/off of a check button ?notch filter auto correction? . 2008/07 - 25 -
[AKD4373-B] 8-3.indication of a frequency characteristic a frequency characteristic is displayed when [frequency re sponse] button is clicked. the register values are updated at the same time. if ?frequency range? is changed, and [update] button is clicked, indication of a frequency characteristic is updated. figure 23. a frequency characteristic indication result in the following cases, a register set values are updated. (1) when [register setting] button was pushed. (2) when [frequency response] button was pushed. (3) when [update] button was pushed on a frequency characteristic indication window. (4) when set on/off of a check button ?notch filter auto correction? . 8-4. automatic compensation for c enter frequency of a notch filter when a gain of 5 band equalizer is set to ?-1?, equalizer becomes a notch filter. when center frequency of several notch filters are near frequency each other, center frequency error occurs ( figure 24 ). when ?notch filter auto correction? button is checked, automatic compensation is executed for center frequency of a notch filter. register setting and frequency characteristics are displayed after automatic compensation ( figure 25 ). this automatic compensation is available for equalizer band where a gain is set to ?-1?. (note) when distance among center frequencies is smaller th an band width, there is a possibility that automatic compensation does not operate normally. please confirm a compensation result by indication of a frequency characteristic. 2008/07 - 26 -
[AKD4373-B] setting of center frequency: 4400hz, 5000hz, 5400hz / band width: 200hz (3 band common) figure 24. when there is no compensation of center frequency setting of center frequency: 4400hz, 5000hz, 5400hz / band width: 200hz (3 band common) figure 25. when there is compensation of center frequency 2008/07 - 27 -
[AKD4373-B] revision history date (yy/mm/dd) manual revision board revision reason page contents 08/01/18 km091600 0 first edition 08/06/20 parts change 1 board revision: rev.0 rev.1 ak4373: rev. a rev. b 08/06/25 km091601 error correction 11 figure 9 was changed. r10, r11: 0 ? 20k ? 08/07/01 km091602 1 error correction 2 port2 and port3 were exchanged. important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. 2008/07 - 28 -
a a b b c c d d e e e e d d c c b b a a sdti dvdd lrck bick mcki csn cclk cdti pdn avdd-reg hvdd-reg ack title size document number rev date: sheet of ak4373 1 AKD4373-B a3 13 friday, june 20, 2008 title size document number rev date: sheet of ak4373 1 AKD4373-B a3 13 friday, june 20, 2008 title size document number rev date: sheet of ak4373 1 AKD4373-B a3 13 friday, june 20, 2008 hvcm gnd hp spn + c14 1u + c14 1u r3 100 r3 100 jp5 hpl cap-less jp5 hpl cap-less tp8 hpl- tp8 hpl- 1 + c10 1u + c10 1u tp10 hpr- tp10 hpr- 1 j4 l/r out j4 l/r out 4 6 3 c2 0.1u c2 0.1u + c11 47u + c11 47u + c13 1u + c13 1u + c1 10u + c1 10u j2 hp j2 hp 4 6 3 jp1 i2c-sel jp1 i2c-sel r7 51 r7 51 r1 10k r1 10k tp9 hpr+ tp9 hpr+ 1 tp7 hpl+ tp7 hpl+ 1 c3 4.7n c3 4.7n j3 min+/- j3 min+/- 6 4 3 + c12 47u + c12 47u c5 0.1u c5 0.1u r11 20k r11 20k + c4 10u + c4 10u r13 47k r13 47k j1 spk/hpr j1 spk/hpr 4 6 3 + c16 1u + c16 1u r10 20k r10 20k r9 0 r9 0 r4 51 r4 51 jp2 hp/spk-sel jp2 hp/spk-sel r6 51 r6 51 tp1 mcko tp1 mcko 1 r5 51 r5 51 + c6 10u + c6 10u r8 0 r8 0 u5 ak4373 u5 ak4373 nc 1 vcom 2 vss1 3 avdd 4 vcoc 5 i2c 6 pdn 7 csn/cad0 8 cclk/scl 9 cdti/sda 10 sdti 11 lrck 13 bick 14 dvdd 15 vss3 16 mcki 17 mcko 18 spn/hpr-/hvcm 19 spp/hpr+/test 20 hvdd 21 vss2 22 hpr/hpl- 23 rout 26 lout 27 min+ 28 min- 29 nc 30 nc 31 nc 32 nc 12 hpl/hpl+ 24 mutet 25 jp4 hp-sel jp4 hp-sel r14 220 r14 220 jp3 hpr cap-less jp3 hpr cap-less r2 47k r2 47k c7 0.1u c7 0.1u r15 220 r15 220 + c9 2.2u + c9 2.2u r12 47k r12 47k c8 0.1u c8 0.1u + c15 1u + c15 1u - 29 -
a a b b c c d d e e e e d d c c b b a a gnd gnd d-reg d-reg cdti cclk csn mcki sdti lrck bick pdn d-reg dvdd d-reg avdd-reg hvdd-reg dvdd ack title size document number rev date: sheet of clock 1 AKD4373-B a2 33 friday, november 30, 2007 title size document number rev date: sheet of clock 1 AKD4373-B a2 33 friday, november 30, 2007 title size document number rev date: sheet of clock 1 AKD4373-B a2 33 friday, november 30, 2007 up-i/f csn scl/cclk sda/cdti sdti mclk lrck bick cdto lh 3-wire i2c u3 74hc14 u3 74hc14 1a 1 1y 2 2a 3 2y 4 3a 5 3y 6 vcc 14 gnd 7 4y 8 4a 9 5y 10 5a 11 6y 12 6a 13 c24 0.1u c24 0.1u r29 0 r29 0 r21 10k r21 10k jp15 cad0 jp15 cad0 x1 11.2896mhz x1 11.2896mhz 1 2 + c17 47u + c17 47u r19 12k r19 12k r20 5.1 r20 5.1 r25 10k r25 10k r26 470 r26 470 r28 10 r28 10 r23 10k r23 10k r17 1k r17 1k port1 torx141 port1 torx141 out 1 vcc 3 gnd 2 r24 470 r24 470 c31 0.1u c31 0.1u gnd t45-black gnd t45-black 1 jp10 dvdd-reg jp10 dvdd-reg u4 74avc8t245 u4 74avc8t245 a1 3 a2 4 a4 6 a5 7 a6 8 a7 9 a8 10 oe 22 b1 21 b2 20 b3 19 b4 18 b5 17 b6 16 b7 15 b8 14 vccb 24 gnd 13 a3 5 dir 2 vccb 23 vcca 1 gnd 11 gnd 12 c19 0.1u c19 0.1u c22 0.1u c22 0.1u + c20 47u + c20 47u c26 10p c26 10p c18 0.1u c18 0.1u l23 10u l23 10u 1 2 port3 port3 1 2 3 4 5 6 7 8 9 10 + c23 10u + c23 10u jp13 lrck jp13 lrck led1 erf led1 erf k a r18 470 r18 470 r16 10k r16 10k d1 hsu119 d1 hsu119 k a c28 0.1u c28 0.1u sw1 dac/dir_pdn sw1 dac/dir_pdn 2 1 3 u2 ak4116 u2 ak4116 rx0 1 dvdd 2 dvss 3 xti 4 xto 5 lrck 6 bick 7 sdto 8 daux 9 mcko 10 cdto 11 cdti 12 cclk 13 csn 14 int1 15 int0 16 pdn 17 avss 18 r 19 avdd 20 c21 0.1u c21 0.1u tp6 xti tp6 xti 1 c30 0.1u c30 0.1u r30 0 r30 0 l20 10u l20 10u 1 2 + c27 10u + c27 10u c32 0.1u c32 0.1u jp17 bick2 jp17 bick2 t21 ta48033f t21 ta48033f in out gnd +5v t45-red +5v t45-red 1 port2 dsp port2 dsp 1 2 3 4 5 6 7 8 9 10 r22 470 r22 470 jp16 lrck2 jp16 lrck2 r27 10k r27 10k jp18 sda jp18 sda jp12 bick jp12 bick jp14 sdto jp14 sdto jp11 mclk jp11 mclk c29 0.1u c29 0.1u c25 10p c25 10p - 30 -
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